1. Field of the Invention
The present invention relates to a programable logic array (PLA), and particularly to the composition of such a PLA.
2. Description of the Prior Art
A PLA is mainly used for a control circuit or a decoder circuit in a logic large scale integrated circuit (LSI).
FIG. 1 is a diagram of PLA 100 which is used conventionally. In this diagram, reference characters P.sub.1, P.sub.2, P.sub.3, P.sub.4 and P.sub.5 designate P channel MOS transistors (PMOS transistors), and N.sub.1, N.sub.2, N.sub.3, . . . and N.sub.8 designate N channel MOS transistors (NMOS transistors). To one end terminal (source) of each PMOS transistor is connected a power source V.sub.DD. Some of the NMOS transistors comprise an AND array and the others comprise an OR array. PLA 100 is mainly comprised of PMOS and NMOS transistors, product term lines l.sub.1, l.sub.2, l.sub.3 and output lines l.sub.4, l.sub.5 which respectively connect these transistors.
Next, the operation of PLA 100 will be described. The gate terminal of each PMOS transistor is grounded. Thus, the PMOS transistors act as load transistors for the product term lines l.sub.1, l.sub.2, l.sub.3 of the AND array and the output lines l.sub.4, l.sub.5 of the OR array. Accordingly, each level of the product term lines l.sub.1, l.sub.2, l.sub.3 is determined in the AND array by levels of inputs x.sub.1, x.sub.2. Each level of the product term lines l.sub.1, l.sub.2, l.sub.3 is transmitted to the OR array. Thereby, levels of the output lines l.sub.4, l.sub.5 are determined, and outputs f.sub.1, f.sub.2 are obtained. In this case, a stationary current (direct current) flows from each power source V.sub.DD to the ground while the product term lines l.sub.1, l.sub.2, l.sub.3 and the output lines l.sub.4, l.sub.5 are at a LOW (L) level. For example, when the input x.sub.1 is at a HIGH (H) level, the NMOS transistor N.sub.1 is ON. As a result, a fired current flows from the power source V.sub.DD to the ground connected to one end terminal of the NMOS transistor N.sub.1 through the PMOS transistor P.sub.1.
Thus, a fixed current flows from each power source V.sub.DD to the ground, while the terminal term lines and the output lines are at L level.
Accordingly, consumption of electric power in the entire PLA 100 becomes excessive.
FIG. 2 shows a diagram of a synchronous PLA system 200 which is used conventionally. In this diagram, reference characters .phi..sub.1, .phi..sub.2 designate clocks for controlling operation of PLA 200, and these have respectively different phases. An AND array mainly comprises of product term lines 261 and NMOS transistors 267. While an OR array mainly comprises output lines 262 and NMOS transistors 268.
Next, operation of the synchronous PLA system 200 having the above composition will be described with reference to a timing chart shown in FIG. 3.
First, the clock .phi..sub.1 goes to the L level, and precharge of the product term lines 261 is performed. Then, the clock .phi..sub.1 goes to the H level, and the output of the product term lines 261 is provided. Thereafter, the clock .phi..sub.2 goes to the L level, and precharge of the output lines 262 is performed. Subsequently, the clock .phi..sub.2 go to the H level, and the output of the output lines 262 is provided. As the result, outputs f.sub.1 and f.sub.2 are obtained.
In such a manner, the precharge and discharge (output) of the product term lines 261 and the output lines 262 occur respectively by using the clocks .phi..sub.1, .phi..sub.2 having different phases.
As compared with PLA 100 shown in FIG. 1, the synchronous PLA system 200 is such that a fixed current does not flow from the power source V.sub.DD to the ground. Thus, the system has the advantage that consumption of electric power to be used therein can be reduced. However, the synchronous PLA system 200 requires clocks .phi..sub.1, .phi..sub.2 of two phases, and the two phases of the clocks should be set so as to not be the same. Particularly, in a microprocessor which requires high-speed operation, the frequencies of the clocks should be made higher. However, in such a case, it is technically difficult to shorten the clock periods of the clocks .phi..sub.1, .phi..sub.2 without making the phases close to each other.